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max9248/max9250 27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated? website at www.maximintegrated.com. general description the max9248/max9250 digital video serial-to-parallelconverters deserialize a total of 27 bits during data and control phases. in the data phase, the lvds serial input is converted to 18 bits of parallel video data and in the con- trol phase, the input is converted to 9 bits of parallel con- trol data. the separate video and control phases take advantage of video timing to reduce the serial-data rate. the max9248/max9250 pair with the max9247 serializer to form a complete digital video transmission system. for operating frequencies less than 35mhz, the max9248/ max9250 can also pair with the max9217 serializer. the max9248 features spread-spectrum capability, allowing output data and clock to spread over a speci- fied frequency range to reduce emi. the data and clock outputs are programmable for a spectrum spread of ?% or ?%. the max9250 features output enable input control to allow data busing. proprietary data decoding reduces emi and provides dc balance. the dc balance allows ac-coupling, pro- viding isolation between the transmitting and receiving ends of the interface. the max9248/max9250 feature a selectable rising or falling output latch edge. esd tolerance is specified for iso 10605 with ?0kv contact discharge and ?0kv air-gap discharge. the max9248/max9250 operate from a +3.3v ?0% core supply and feature a separate output supply for interfacing to 1.8v to 3.3v logic-level inputs. these devices are available in a 48-lead lqfp package and are specified from -40? to +85? or -40? to +105?. applications navigation system displaysin-vehicle entertainment systems video cameras lcd displays features ? programmable ?% or ?% spread-spectrumoutput for reduced emi (max9248) ? proprietary data decoding for dc balance andreduced emi ? control data deserialized during video blanking ? five control data inputs are single-bit-errortolerant ? output transition time is scaled to operatingfrequency for reduced emi ? staggered output switching reduces emi ? output enable allows busing of outputs(max9250) ? clock pulse stretch on lock ? wide ?% reference clock tolerance ? synchronizes to max9247 serializer withoutexternal control ? iso 10605 and iec 61000-4-2 level 4esd protection ? separate output supply allows interface to 1.8vto 3.3v logic ? +3.3v core power supply ? space-saving lqfp package ? -40? to +85? and -40? to +105? operatingtemperature ranges part temp range pin-package max9248 ecm+ -40 c to +85 c 48 lqfp max9248ecm/v+ -40 c to +85 c 48 lqfp MAX9248GCM+ -40 c to +105 c 48 lqfp MAX9248GCM/v+ -40 c to +105 c 48 lqfp max9250 ecm+ -40 c to +85 c 48 lqfp max9250ecm/v+ -40 c to +85 c 48 lqfp max9250gcm+ -40 c to +105 c 48 lqfp max9250gcm/v+ -40 c to +105 c 48 lqfp ordering information 19-3943; rev 4; 7/14 + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. pin configuration appears at end of data sheet. downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers 2 maxim integrated max9248/max9250 absolute maximum ratings dc electrical characteristics(v cc_ = +3.0v to +3.6v, pwrdwn = high, differential input voltage ? v id ? = 0.05v to 1.2v, input common-mode voltage v cm = ? v id / 2 ? to v cc - ? v id / 2 ? , t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, ? v id ? = 0.2v, v cm = 1.2v, t a = +25?.) (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc_ to _gnd........................................................-0.5v to +4.0v any ground to any ground...................................-0.5v to +0.5v in+, in- to lvdsgnd............................................-0.5v to +4.0v in+, in- short circuit to lvdsgnd or v cclvds ........continuous (r/ f , outen, rng_, refclk, ss pwrdwn ) to gnd................................. -0.5v to (v cc + 0.5v) (rgb_out[17:0], cntl_out[8:0], de_out, pclk_out, lock ) to v ccognd .............................-0.5v to (v cco + 0.5v) continuous power dissipation (t a = +70?) 48-lead lqfp (derate 21.7mw/? above +70?).....1739mw esd protection machine model (r d = 0 , c s = 200pf) all pins to gnd............................................................ 200v human body model (r d = 1.5k , c s = 100pf) all pins to gnd.............................................................. 2kv iso 10605 (r d = 2k , c s = 330pf) contact discharge (in+, in-) to gnd ............................ 10kv air-gap discharge (in+, in-) to gnd ............................ 30kv iec 61000-4-2 (r d = 330 , c s = 150pf) contact discharge (in+, in-) to gnd ............................ 10kv air-gap discharge (in+, in-) to gnd ............................ 15kv storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units single-ended inputs (r/ f , outen, rng0, rng1, refclk, pwrdwn , ss) high-level input voltage v ih 2.0 v cc + 0.3 v low-level input voltage v il -0.3 +0.8 v v i n = - 0.3v to 0 ( m ax 9248/ m ax 9250e c m ) , v i n = - 0.15v to 0 ( m ax 9248/ m ax 9250g c m ) , -100 +20 input current i in pwrdwn = high or low v in = 0 to (v cc + 0.3v) -20 +20 ? input clamp voltage v cl i cl = -18ma -1.5 v single-ended outputs (rgb_out[17:0], cntl_out[8:0], de_out, pclk_out, lock ) i oh = -100? v cco - 0.1 i oh = -2ma, rng1 = high v cco - 0.35 high-level output voltage v oh i oh = -2ma, rng1 = low v cco - 0.4 v i ol = 100? 0.1 i ol = 2ma, rng1 = high 0.3 low-level output voltage v ol i ol = 2ma, rng1 = low 0.35 v high-impedance output current i oz pwrdwn = low or outen = low, v o = -0.3v to (v cco + 0.3v) -10 +10 ? rng1 = high, v o = 0 -10 -50 output short-circuit current i os rng1 = low, v o = 0 -7 -40 ma downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers maxim integrated 3 max9248/max9250 dc electrical characteristics (continued)(v cc_ = +3.0v to +3.6v, pwrdwn = high, differential input voltage ? v id ? = 0.05v to 1.2v, input common-mode voltage v cm = ? v id / 2 ? to v cc - ? v id / 2 ? , t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, ? v id ? = 0.2v, v cm = 1.2v, t a = +25?.) (notes 1, 2) parameter symbol conditions min typ max units lvds input (in+, in-) differential input high threshold v th (note 3) 50 mv differential input low threshold v tl (note 3) -50 mv input current i in+ , i in- pwrdwn = high or low (note 3) -40 +40 ? max9248/max9250ecm 42 60 78 pwrdwn = high or low max9248/max9250gcm 42 60 88 max9248/max9250ecm 42 60 78 input bias resistor (note 3) r ib v cc_ = 0 or open,pwrdwn = 0 or open,figure 1 max9248/max9250gcm 42 60 88 k power-off input current i ino+ , i ino- v cc_ = 0 or open, pwrdwn = 0 or open (note 3) -60 +60 ? power supply 2.5mhz 19 rng1 = lowrng0 = low 5mhz 33 5mhz 28 rng1 = lowrng0 = high 10mhz 49 10mhz 33 rng1 = highrng0 = low 20mhz 59 20mhz 45 max9250c l = 8pf, worst-casepattern, figure 2 rng1 = highrng0 = high 42mhz 89 2.5mhz 31 rng1 = lowrng0 = low 5mhz 48 5mhz 40 rng1 = lowrng0 = high 10mhz 70 10mhz 49 rng1 = highrng0 = low 20mhz 87 20mhz 68 35mhz 100 worst-case supply current max9248c l = 8pf, worst-casepattern, figure 2 rng1 = highrng0 = high 42mhz 120 ma power-down supply current i ccz (note 4) 50 ? downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers 4 maxim integrated max9248/max9250 ac electrical characteristics(v cc_ = +3.0v to +3.6v, c l = 8pf, pwrdwn = high, differential input voltage ? v id ? = 0.1v to 1.2v, input common-mode voltage v cm = ? v id / 2 ? to v cc - ? v id / 2 ? , t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, ? v id ? = 0.2v, v cm = 1.2v, t a = +25?.) (notes 3, 5) parameter smbol conditions min tp max units refclk timing requirements max9248/max9250ecm 23.8 400.0 period t t max9248/max9250gcm 28.6 400.0 ns max9248/max9250ecm 2.5 42.0 frequency f clk max9248/max9250gcm 2.5 35.0 mhz frequency variation f clk refclk to serializer pclk_in, worst-case output pattern (figure 2) -2.0 +2.0 % duty cycle dc 40 50 60 % transition time t tran 20% to 80% 6 ns switching characteristics max9248/ max9250ecm 2.2 4.6 rng1 = high max9248/ max9250gcm 2.2 4.9 max9248/ max9250ecm 2.8 5.2 output rise time t r figure 3 rng1 = low max9248/ max9250gcm 2.8 6.1 ns rng1 = high max9248/ max9250ecm 1.9 4.0 max9248/ max9250ecm 2.3 4.3 output fall time t r figure 3 rng1 = low max9248/ max9250gcm 2.3 5.2 ns pclk_out high time t high figure 4 0.4 x t t 0.45 x t t 0.6 x t t ns pclk_out low time t low figure 4 0.4 x t t 0.45 x t t 0.6 x t t ns data valid before pclk_out t dvb figure 5 0.35 x t t 0.4 x ns data valid after pclk_out t dva figure 5 0.35 x t t 0.4 x ns max9248, figure 8 33,600 x t t pll lock to refclk t pllref max9250, figure 7 16,928 x t t ns downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers maxim integrated 5 max9248/max9250 note 1: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to groundexcept v th and v tl . note 2: maximum and minimum limits over temperature are guaranteed by design and characterization. devices are productiontested at t a = +25?. note 3: parameters are guaranteed by design and characterization, and are not production tested. limits are set at 6 sigma. note 4: all lvttl/lvcmos inputs, except pwrdwn at 0.3v or v cc - 0.3v. pwrdwn is 0.3v, refclk is static. note 5: c l includes probe and test jig capacitance. ac electrical characteristics (continued)(v cc_ = +3.0v to +3.6v, c l = 8pf, pwrdwn = high, differential input voltage ? v id ? = 0.1v to 1.2v, input common-mode voltage v cm = ? v id / 2 ? to v cc - ? v id / 2 ? , t a = -40? to +105?, unless otherwise noted. typical values are at v cc_ = +3.3v, ? v id ? = 0.2v, v cm = 1.2v, t a = +25?.) (notes 3, 5) parameter smbol conditions min tp max units maximum output frequency f refclk + 3.6% f refclk + 4.0% f refclk + 4.4% ss = high, figure 11 minimum output frequency f refclk - 4.4% f refclk - 4.0% f refclk - 3.6% maximum output frequency f refclk + 1.8% f refclk + 2.0% f refclk + 2.2% spread-spectrum output frequency (max9248) f pclk_out ss = low, figure 11 minimum output frequency f refclk - 2.2% f refclk - 2.0% f refclk - 1.8% mhz spread-spectrum modulation frequency f ssm figure 11 f refclk / 1024 khz power-down delay t pdd figures 7, 8 100 ns ss change delay t sspll max9248, figure 17 32,800 x t t ns output enable time t oe max9250, figure 8 10 30 ns output disable time t oz max9250, figure 9 10 30 ns downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers 6 maxim integrated max9248/max9250 worst-case pattern supply current vs. frequency max9248/50 toc01 frequency (mhz) supply current (ma) 35 30 510152025 10 20 30 40 50 60 70 0 04 0 4 5 max9248 max9250 output transition time vs. output supply voltage (v cco ) max9248/50 toc02 output supply voltage (v) output transition time (ns) 3.0 2.7 2.4 2.1 1 2 3 4 5 60 1.8 3.3 rng1 = high t r t f output transition time vs. output supply voltage (v cco ) max9248/50 toc03 output supply voltage (v) output transition time (ns) 3.0 2.7 2.4 2.1 4 5 61 2 3 7 8 9 10 0 1.8 3.3 rng1 = low t r t f output power spectrum vs. frequency (refclk = 42mhz, no spread, 4%, and 2% spread) max9248/50 toc04 frequency (mhz) power spectrum (dbm) 43 44 42 41 40 -30 -20 -10-60 -50 -40 0 -70 39 45 no spread resolution bw = 30khz video bw = 100khz 2% spread 4% spread bit-error rate vs. cable length max9248/50 toc05 cat5 cable length (m) bit-error rate 810 6 4 2 1.00e-141.00e-13 1.00e-12 1.00e-11 1.00e-10 01 2 refclk = 42mhz840mbps data rate for cable length < 10m ber < 10 -12 cat5 cable cable length vs. frequency bit-error rate < 10 -9 max9248/50 toc06 cable length (m) frequency (mhz) 25 3010 15 20 35 40 45 5 18 16 14 12 10 8642 02 0 typical operating characteristics (v cc _ = +3.3v, c l = 8pf, t a = +25?, unless otherwise noted.) downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers maxim integrated 7 max9248/max9250 pin description pin max9248 max9250 name function 11 r / f rising or falling latch edge select. lvttl/lvcmos input. selects the edge of pclk_outfor latching data into the next chip. set r/ f = high for a rising latch edge. set r/ f = low for a falling latch edge. internally pulled down to gnd. 2 2 rng1 lvttl/lvcmos range select input. set to the range that includes the serializer parallel clock input frequency. internally pulled down to gnd. 33v cclvds lv d s s up p l y v ol tag e. byp ass to lv d s g n d w i th 0.1? and 0.001? cap aci tor s i n p ar al l el as cl ose to the d evi ce as p ossi b l e, w i th the sm al l est val ue cap aci tor cl osest to the sup p l y p i n. 4 4 in+ noninverting lvds serial-data input 5 5 in- inverting lvds serial-data input 66 lvdsgnd lvds supply ground 7 7 pllgnd pll supply ground 88v ccpll pll supply voltage. bypass to pllgnd with 0.1? and 0.001? capacitors in parallel asclose to the device as possible with the smallest value capacitor closest to the supply pin. 9 9 rng0 lvttl/lvcmos range select input. set to the range that includes the serializer parallel clock input frequency. internal pulldown to gnd. 10 10 gnd digital supply ground 11 11 v cc digital supply voltage. supply for lvttl/lvcmos inputs and digital circuits. bypass tognd with 0.1? and 0.001? capacitors in parallel as close to the device as possible with the smallest value capacitor closest to the supply pin. 12 12 refclk lvttl/lvcmos reference clock input. apply a reference clock that is within 2% of the serializer pclk_in frequency. internally pulled down to gnd. 13 13 pwrdwn lvttl/lvcmos power-down input. internally pulled down to gnd. 14 ss lv ttl/lv c m os s p r ead - s p ectr um inp ut. s s sel ects the fr eq uency sp r ead of p c lk_o u t and outp ut d ata r el ati ve to p c lk_in . d r i ve s s hi g h for 4% sp r ead and p ul l l ow for 2% sp r ead . 15?3 15?3 cntl_out0 cntl_out8 lvttl/lvcmos control data outputs. cntl_out[8:0] are latched into the next chip on the rising or falling edge of pclk_out as selected by r/ f when de_out is low, and are held at the last state when de_out is high. 24 24 de_out lvttl/lvcmos data-enable output. high indicates rgb_out[17:0] are active. lowindicates cntl_out[8:0] are active. 25, 37 25, 37 v ccognd output supply ground 26, 38 26, 38 v cco output supply voltage. bypass to gnd with 0.1? and 0.001? capacitors in parallel asclose to the device as possible with the smallest value capacitor closest to the supply pin. downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers 8 maxim integrated max9248/max9250 functional diagram in+in- refclk ser-to-par timing and control pll dc balance/ decode 1 0 rgb_outlock pwrdwn ss pclk_out de_out cntl_out sspll fifo rng[0:1] r/f rng[0:1] in+in- refclk ser-to-par timing and control pll dc balance/ decode 1 0 outenrgb_out lock pwrdwn ref_in pclk_out de_out cntl_out r/f max9250 max9248 pin description (continued) pin max9248 max9250 name function 27 27 lock lvttl/lvcmos lock indicator output. outputs are valid when lock is low. 28 28 pclk_out lv ttl/lv c m os p ar al lel cl ock outp ut. latches d ata i nto the next chi p on the ed g e selected b y r/ f . 29?6, 39?8 29?6, 39?8 rgb_out0 rbg_out7, rgb_out8 rgb_out17 lvttl/lvcmos red, green, and blue digital video data outputs. rgb_out[17:0] arelatched into the next chip on the edge of pclk_out selected by r/ f when de_out is high, and are held at the last state when de_out is low. 14 outen lvttl/lvcmos output enable input. high activates the single-ended outputs. drivinglow places the single-ended outputs in high impedance except lock . internally pulled down to gnd. downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers maxim integrated 9 max9248/max9250 pclk_out pclk_out shown for r/f = high (rising latch edge) t dvb t dva 2.0v 2.0v 2.0v 0.8v 0.8v 0.8v de_out lock rgb_out[17:0] cntl_out[8:0] figure 5. synchronous output timing in+, in- pclk_out cntl_out rgb_out 20 serial bits serial-word n serial-word n + 1 parallel-word n - 1 parallel-word n t delay pclk_out shown for r/f = high figure 6. deserializer delay pclk_out t low t high 2.0v 0.8v figure 4. high and low times de_out lock pclk_out rgb_out[17:0] cntl_out[8:0] 0.9 x v cco 0.1 x v cco t f t r figure 3. output rise and fall times lvdsreceiver 1.2v in+ r ib r ib in- figure 1. lvds input bias pclk_out odd rgb_out cntl_out even rgb_out cntl_out rising latch edge shown (r/f = high). figure 2. worst-case output pattern downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers 10 maxim integrated max9248/max9250 pwrdwn refclk pclk_out rgb_out cntl_out de_out lock t pllref transition word found recovered clock clock stretch valid data high impedance high impedancehigh impedance high impedance high impedancehigh impedance note: r/f = high t pdd 0.8v 2.0v figure 7. pll lock to refclk and power-down delay for max9250 pwrdwn refclk pclk_out rgb_out cntl_out de_out lock t pllref transition word found output clock spread clock stretch valid data high impedance high impedancehigh impedance high impedance high impedancehigh impedance note: r/f = high t pdd 0.8v 2.0v 288 clock cycles output data spread figure 8. pll lock to refclk and power-down delay for max9248 downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers maxim integrated 11 max9248/max9250 outen active high impedance de_out rgb_out[17:0] cntl_out[8:0] t oe 0.8v max9250 figure 9. output enable time outen high impedance active de_out rgb_out[17:0] cntl_out[8:0] t oz 2.0v max9250 figure 10. output disable time frequency time f rxclkout (max) f rxclkin f rxclkout (min) 1 / f ssm figure 11. simplified modulation profile downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers 12 maxim integrated max9248/max9250 detailed description the max9248/max9250 dc-balanced deserializersoperate at a 2.5mhz-to-42mhz parallel clock frequen- cy, deserializing video data to the rgb_out[17:0] out- puts when the data-enable output de_out is high, or control data to the cntl_out[8:0] outputs when de_out is low. the outputs on the max9248 are pro- grammable for ?% or ?% spread relative to the lvds input clock frequency, while the max9250 has no spread, but has an output-enable input that allows out- put busing. the video phase words are decoded using two overhead bits, en0 and en1. control phase words are decoded with one overhead bit, en0. encoding, performed by the max9247 serializer, reduces emi and maintains dc balance across the serial cable. the seri- al-input word formats are shown in tables 1 and 2. control data inputs c0 to c4, each repeated over three serial bit times by the serializer, are decoded using majority voting. two or three bits at the same state determine the state of the recovered bit, providing sin- gle bit-error tolerance for c0 to c4. the state of c5 to c8 is determined by the level of the bit itself (no voting is used). ac-coupling benefits ac-coupling increases the input voltage of the lvdsreceiver to the voltage rating of the capacitor. two capacitors are sufficient for isolation, but four capaci- tors?wo at the serializer output and two at the deseri- alizer input?rovide protection if either end of the cable is shorted to a high voltage. ac-coupling blocks low-frequency ground shifts and common-mode noise. the max9247 serializer can also be dc-coupled to themax9248/max9250 deserializers. figures 12 and 14 show the ac-coupled serializer and deserializer with two capacitors per link, and figures 13 and 15 show the ac-coupled serializer and deserializer with four capacitors per link. applications information selection of ac-coupling capacitors see figure 16 for calculating the capacitor values forac-coupling depending on the parallel clock frequen- cy. the plot shows capacitor values for two- and four- capacitor-per-link systems. for applications using less than 18mhz clock frequency, use 0.1? capacitors. termination and input bias the in+ and in- lvds inputs are internally connectedto +1.2v through 42k (min) to provide biasing for ac- coupling (figure 1). assuming 100 interconnect, the lvds input can be terminated with a 100 resistor. match the termination to the differential impedance ofthe interconnect. use a thevenin termination, providing 1.2v bias, on an ac-coupled link in noisy environments. for intercon- nect with 100 differential impedance, pull each lvds line up to v cc with 130 and down to ground with 82 at the deserializer input (figures 12 and 15). this termi-nation provides both differential and common-mode termination. the impedance of the thevenin termination should be half the differential impedance of the inter- connect and provide a bias voltage of 1.2v. 01234567891 01 11 21 31 41 51 61 71 8 19 en0 en1 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 bit 0 is the lsb and is deserialized first. en[1:0] are encoding bits. s[17:0] are encoded symbols. table 1. serial video phase word format 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 e n 0 c0 c0 c0 c1 c1 c1 c2 c2 c2 c3 c3 c3 c4 c4 c4 c5 c6 c7 c8 bit 0 is the lsb and is deserialized first. c[8:0] are the mapped control inputs. table 2. serial control phase word format downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers maxim integrated 13 max9248/max9250 par-to-ser timing and control pll dc balance/ encode input latch rgb_in cntl_in de_in pclk_in rng0 rng1 pwrdwn 1 0 130 v cc 130 in out 82 82 rng1 rng0 ser-to-par timing and control pll dc balance/ decode 1 0 outenrgb_out lock pwrdwn ref_in pclk_out de_out cntl_out ceramic rf surface-mount capacitor 100 differential stp cable *capacitors can be at either end. ** r/f cmf pre max9250 max9247 figure 12. ac-coupled max9247 serializer and max9250 deserializer with two capacitors per link par-to-ser timing and control pll dc balance/ encode input latch rgb_in cntl_in de_in pclk_in rng0 rng1 pwrdwn 1 0 130 v cc 130 in out 82 82 rng1 rng0 ser-to-par timing and control pll dc balance/ decode 1 0 outenrgb_out lock pwrdwn ref_in pclk_out de_out cntl_out ceramic rf surface-mount capacitor 100 differential stp cable cmf pre r/f max9250 max9247 figure 13. ac-coupled max9247 serializer and max9250 deserializer with four capacitors per link downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers 14 maxim integrated max9248/max9250 par-to-ser timing and control dc balance/ encode input latch rgb_in cntl_in de_in pclk_in rng0 rng1 pwrdwn 1 0 130 v cc 130 in+in- out 82 82 cmf pre refclk ser-to-par timing and control pll dc balance/ decode 1 0 rgb_out lock pwrdwn ss pclk_out de_out cntl_out ceramic rf surface-mount capacitor 100 differential stp cable pll * * *capacitors can be at either end. sspll fifo rng[0:1] r/f max9248 max9247 figure 14. ac-coupled max9247 serializer and max9248 deserializer with two capacitors per link par-to-ser timing and control dc balance/ encode input latch rgb_in cntl_in de_in pclk_in rng0 rng1 pwrdwn 1 0 130 v cc 130 in+in- out 82 82 cmf pre refclk ser-to-par timing and control pll dc balance/ decode 1 0 rgb_out lock pwrdwn ss pclk_out de_out cntl_out ceramic rf surface-mount capacitor 100 differential stp cable pll sspll fifo rng[0:1] r/f max9248 max9247 figure 15. ac-coupled max9247 serializer and max9248 deserializer with four capacitors per link downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers maxim integrated 15 max9248/max9250 input frequency detection a frequency-detection circuit detects when the lvdsinput is not switching. when not switching, all outputs except lock are low, lock is high, and pclk_out follows refclk. this condition occurs, for example, ifthe serializer is not driving the interconnect or if the interconnect is open. frequency range setting (rng[1:0]) the rng[1:0] inputs select the operating frequencyrange of the max9248/max9250 and the transition time of the outputs. select the frequency range that includes the max9247 serializer pclk_in frequency. table 3 shows the selectable frequency ranges and the corre- sponding data rates and output transition times. power down driving pwrdwn low puts the outputs in high imped- ance and stops the pll. with pwrdwn 0.3v and all lvttl/lvcmos inputs 0.3v or v cc - 0.3v, the sup- ply current is reduced to less than 50?. drivingpwrdwn high initiates lock to the local reference clock (refclk) and afterwards to the serial input. lock and loss-of-lock ( lock ) when pwrdwn is driven high, the pll begins locking to refclk, drives lock from high impedance to high and the other outputs from high impedance to low,except pclk_out. pclk_out outputs refclk while the pll is locking to refclk. lock to refclk takes a maximum of 16,928 refclk cycles for the max9250. the max9248 has an additional spread-spectrum pll (sspll) that also begins locking to refclk. locking both plls to refclk takes a maximum of 33,600 refclk cycles for the max9248. when the max9248/max9250 complete their lock torefclk, the serial input is monitored for a transition word. when a transition word is found, lock output is driven low, indicating valid output data and the parallelrate clock recovered from the serial input is output on pclk_out. the max9248 sspll waits an additional 288 clock cycles after the transition word is found before lock is driven low and sequence takes effect. pclk_out is stretched on the change from refclk torecovered clock (or vice versa) at the time when the transition word is found. if a transition word is not detected within 2 22 cycles of pclk_out, lock is driven high, the other outputs except pclk_out are driven low. refclk is output onpclk_out and the deserializer continues monitoring the serial input for a transition word. see figure 7 for the max9250 and figure 8 for the max9248 regarding the synchronization timing diagram. the max9248 input-to-output delay can be as low as (4.5t t + 8.0)ns or as high as (36t t + 16)ns due to spread-spectrum variations (see figure 6).the max9250 input-to-output delay can be as low as (3.575t t + 8)ns or as high as (3.725t t + 16)ns. parallel clock frequency (mhz) capacitor value (nf) 21 24 27 33 36 39 30 120 8060 40 20 100 140 0 18 42 four capacitors per link two capacitors per link rng1 rng0 parallel clock (mhz) serial- data rate (mbps) output transition time 00 2.5 to 5.0 50 to 100 0 1 5 to 10 100 to 200 slow 1 0 10 to 20 200 to 400 1 1 20 to 42 400 to 840 fast figure 16. ac-coupling capacitor values vs. clock frequency of 18mhz to 42mhz table 3. frequency range programming downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers 16 maxim integrated max9248/max9250 spread-spectrum selection the max9248 single-ended data and clock outputs areprogrammable for a variation of ?% or ?% around the lvds input clock frequency. the modulation rate of the frequency variation is 32khz for a 33mhz lvds clock input and scales linearly with the clock frequency (see table 4). the output spread is controlled through the ss input (see table 5). driving ss high spreads all data and clock outputs by ?%, while pulling low spreads ?%. any spread change causes a delay time of 32,000 x t t before output data is valid. when the spread amount ischanged from ?% to ?% or vice versa, the data out- puts go low for one t sspll delay (see figure 17). the data outputs stay low, but are not valid when thespread amount is changed. output enable (outen) and busing outputs the outputs of two max9250s can be bused to form a2:1 mux with the outputs controlled by the output enable. wait 30ns between disabling one deserializer (driving outen low) and enabling the second one (dri- ving outen high) to avoid contention of the bused out- puts. outen controls all outputs except lock . rising or falling output latch edge (r/ f ) the max9248/max9250 have a selectable rising orfalling output latch edge through a logic setting on r/ f . driving r/ f high selects the rising output latch edge, which latches the parallel output data into the next chipon the rising edge of pclk_out. driving r/ f low selects the falling output latch edge, which latches theparallel output data into the next chip on the falling edge of pclk_out. the max9248/max9250 output- latch-edge polarity does not need to match the max9247 serializer input-latch-edge polarity. select the latch-edge polarity required by the chip being driven by the max9248/max9250. t ? sspll (32,800 x t t ) 4% or 2% spread 4% or 2% spread low ss pclk_out rgb_out[17:0] cntl_out8:0] lock figure 17. output waveforms when spread amount is changed f pclk_in f m (khz) = f pclk_in / 1024 8 7.81 10 9.77 16 15.63 32 31.25 40 39.06 42 41.01 table 4. modulation rate ss input level output spread high data and clock output spread ?%relative to refclk low data and clock output spread ?%relative to refclk table 5. ss function downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers maxim integrated 17 max9248/max9250 staggered and transition time adjusted outputs rgb_out[17:0] are grouped into three groups of six, witheach group switching about 1ns apart in the video phase to reduce emi and ground bounce. cntl_out[8:0] switch during the control phase. output transition times are slower in the 2.5mhz to 5mhz and 5mhz to 10mhz ranges and faster in the 10mhz to 20mhz and 20mhz to 42mhz ranges. data-enable output (de_out) the max9248/max9250 deserialize video and controldata at different times. control data is deserialized during the video blanking time. de_out high indicates that video data is being deserialized and output on rgb_out[17:0]. de_out low indicates that control data is being deserialized and output on cntl_out[8:0]. when outputs are not being updated, the last data received is latched on the outputs. figure 18 shows the de_out timing. power-supply sequencing of max9247 and max9248/max9250 video link the max9247 and max9248/max9250 video link canbe powered up in several ways. the best approach is to keep both max9247 and max9248 powered down while supplies are ramping up and pclk_in of the max9247 and refclk of the max9248/max9250 are stabilizing. after all of the power supplies of the max9247 and max9248/max9250 are stable, including pclk_in and refclk, do the following: power up the max9247 first wiith high-transition density data (e.g., prbs, checkboard) wait for at least t lock of max9247 (or 17100 x t t ) to get activity on the link power up the max9248 power-supply circuits and bypassing there are separate on-chip power domains for digitalcircuits and lvttl/lvcmos inputs (v cc supply and gnd), outputs (v cco supply and v ccognd ), pll (v ccpll supply and pllgnd), and the lvds input (v cclvds supply and lvdsgnd). the grounds are iso- lated by diode connections. bypass each v cc , v cco , v ccpll , and v cclvds pin with high-frequency, sur- face-mount ceramic 0.1? and 0.001? capacitors inparallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. the outputs are powered from v cco , which accepts a 1.71v to 3.6v supply, allowing direct interface to inputswith 1.8v to 3.3v logic levels. cables and connectors interconnect for lvds typically has a differentialimpedance of 100 . use cables and connectors that have matched differential impedance to minimizeimpedance discontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less emi due to magnetic field cancel- ing effects. balanced cables pick up noise as common mode, which is rejected by the lvds receiver. pclk_outcntl_out de_out rgb_out = output data held control data control data video data pclk_out timing shown for r/f = high (rising output latch edge) figure 18. output timing downloaded from: http:///
27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers 18 maxim integrated max9248/max9250 board layout separate the lvttl/lvcmos outputs and lvds inputsto prevent crosstalk. a four-layer pcb with separate lay- ers for power, ground, and signals is recommended. esd protection the max9248/max9250 esd tolerance is rated forhuman body model, machine model, iec 61000-4-2 and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic systems. all lvds inputs on the max9248/max9250 meet iso 10605 esd protection at ?0kv air-gap discharge and ?0kv contact discharge and iec 61000-4-2 esd protection at ?5kv air-gap discharge and ?0kv contact discharge. all other pins meet the human body model esd tolerance of ?kv. the human body model dis- charge components are c s = 100pf and r d = 1.5k (figure 19). the iec 61000-4-2 discharge componentsare c s = 150pf and r d = 330 (see figure 20). the iso 10605 discharge components are c s = 330pf and r d = 2k (figure 21). the machine model discharge compo- nents are c s = 200pf and r d = 0 (figure 22). rgb_out7rgb_out6 rgb_out5 rgb_out4 rgb_out3 rgb_out2 rgb_out1 rgb_out0 pclk_out lock v cco v ccognd 12 3 4 5 6 7 8 9 1011 12 3635 34 33 32 31 30 29 28 27 26 25 pwrdwn ss (outen) cntl_out0 cntl_out1cntl_out2 cntl_out3 cntl_out4 cntl_out5 cntl_out6 cntl_out7 cntl_out8 de_out lqfp max9248/max9250 1314 15 16 17 18 19 20 21 22 23 24 4847 46 45 44 43 42 41 40 39 38 37 rgb_out17rgb_out16 rgb_out15 rgb_out14 rgb_out13 rgb_out12 rgb_out11 rgb_out10 rgb_out9 rgb_out8 v cco v ccognd r/f rng1 v cclvds in+ in- lvdsgnd pllgnd v ccpll rng0 gnd v cc refclk top view pin configuration storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m r d 1.5k c s 100pf figure 19. human body esd test circuit c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r2 330 figure 20. iec 61000-4-2 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2k c s 330pf figure 21. iso 10605 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 0 c s 200pf figure 22. machine model esd test circuit downloaded from: http:///
package type package code outline no. land pattern no. 48 lqfp c48+3 21-0054 90-0093 27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers maxim integrated 19 max9248/max9250 chip information process: cmos package information for the latest package outline information and land patterns, goto www.maximintegrated.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. packagedrawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 20 maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 2014 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. 27-bit, 2.5mhz to 42mhz dc-balanced lvds deserializers max9248/max9250 revision history revision number revision date description pages changed 2 5/08 replaced tqfp and tqfn packages with lqfp package, changed temperat ure limits for +105 c part, and added machines model esd text and diagram 15, 7, 1619 3 4/09 added /v parts in the ordering information table and added new power- supply sequencing of max9247 and max9248/max9250 video link section 1, 17 4 7/14 clarified definition of test conditions and updated package information 4, 17, 19 downloaded from: http:///

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